The present application relates, for example, to a switching power supply apparatus having a resonant switching converter.
Switching power supply apparatuses equipped with a variety of resonant converters are widely used.
A high power conversion efficiency can be easily achieved by a resonant converter, and a low noise characteristics can be also achieved because a switching waveform of the resonant converter is a substantially sinusoidal waveform. In addition, a resonant converter has an advantage of being configurable with a comparatively small number of components.
As a typical configuration of a resonant converter, a configuration employing a half-bridge coupling system, in which a switching circuit composed of two switching elements serially connected is disposed in parallel with a DC input voltage, is widely used. The current resonant converter employing a half-bridge coupling system is configured such that two switching elements alternately turn ON/OFF. In such a switching converter employing a half-bridge coupling system, a combination of each switching element and a resonant capacitor connected in parallel with each other is commonly in use.
Switching drive for a resonant converter is configured such that two switching elements alternately turn ON/OFF, and a transient period during which both switching elements are OFF at the same time is set. This transient period is set to prevent two switching elements from turning ON at the same time.
FIG. 1 shows an example of a switching power supply circuit that uses a current resonant converter employing a half-bridge coupling system as a DC-DC converter 4, where the half-bridge coupling system includes field-effect transistors (hereinafter referred to as FETs accordingly) Q1 and Q2 as switching elements. A commercial power supply is supplied to an AC/DC converter 3 via an AC plug 1 and a fuse 2. The AC/DC converter 3 is composed of a diode bridge BD, and a DC voltage output from the AC/DC converter 3 is supplied to a blocking capacitor (smoothing capacitor) Ci.
A voltage generated across the blocking capacitor Ci is supplied to the DC-DC converter 4 configured as a current resonant converter. In the DC-DC converter 4, a primary series resonant capacitor (hereinafter referred to as a resonant capacitor accordingly) C1 is disposed between one end of a primary coil N1 and the ground. Here, the power supply apparatus shown in FIG. 1 employs the configuration to drive the switching elements by an external excitation.
The DC-DC converter 4 shown in FIG. 1 includes a series connection circuit composed of one FET Q1 and the other FET Q2. In other words, two FETs Q1 and Q2 are coupled in a half-bridge configuration. The half-bridge circuit composed of these FET Q1 and FET Q2 is connected in parallel with a DC input voltage Vdc across the blocking capacitor Ci. Because the FET Q1 and FET Q2 are switching-driven, the DC input voltage Vdc sent to the FET Q1 and FET Q2 is switched.
In addition, a body diode D1 is connected in a so-called antiparallel state with the FET Q1. In other words, the drain of the FET Q1 is connected with the cathode of the body diode D1, and the source of the FET Q1 is connected with the anode of the body diode D1 so that the forward direction of the FET Q1 and the forward direction the body diode are reversed. In a similar way, a body diode D2 is connected in an antiparallel state with the FET Q2. A series resonant circuit, which is composed of a primary coil N1 of a transformer T, a leakage inductance component L1 of the transformer T, and a resonant capacitor C1, is connected in parallel with the FET Q2.
On the other hand, a resonant capacitor is not connected with the FET Q1. However, as is generally familiar, a resonant operation of the configuration with a resonant capacitor connected in parallel with the FET Q2 and without any resonant capacitor connected in parallel with the FET Q1 is similar to that of the configuration with two resonant capacitors connected in parallel with the FET Q1 and FET Q2 respectively.
A control circuit 9 is provided for switching-driving the FET Q1 and FET Q2 by an external excitation, and includes, for example, an oscillator 10 and a drive circuit 11 as shown in FIG. 1. The oscillator 10 generates an oscillating signal with a predefined frequency, and supplies the oscillating signal to the drive circuit 11. The drive circuit 11 generates drive signals SG1 and SG2 for switching-driving the FET Q1 and FET Q2 with the use of the input oscillating signal.
The frequencies of these drive signals SG1 and SG2 are determined on the basis of the output signal of the oscillator 10 input to the drive circuit 11. In addition, there is a phase difference of 180 degrees between the phase of the drive signal SG1 and that of the drive signal SG2. Therefore, the FET Q1 and FET Q2 perform a switching operation in such a way that they turn ON/OFF alternately in accordance with a switching frequency determined by the oscillating signal frequency generated by the oscillating circuit 11.
In addition, the waveforms of the drive signals SG1 and SG2 are formed in such a way that a transient period during which both FET Q1 and FET Q2 are OFF at the same time is set. The control circuit 9 also includes an error amplifier 12 and a photocoupler 13.
The transformer T is provided for transmitting a switching output of the FET Q1 and FET Q2 from the primary side to the secondary side, and is fabricated by winding a primary coil N1 and a secondary coil N2 around a core. In addition, the leakage inductance component L1 contributes to a resonant operation. One end part of the primary coil N1 is connected with the connection node between the FET Q1 and FET Q2, and the other end part is connected with the negative side of the DC input voltage Vdc via the series resonant capacitor C1.
Here, the leakage inductance component L1 is connected in series with the resonant capacitor C1, and this series connection of L1 and C1 forms a primary side series resonant circuit. The switching output of the FET Q1 and FET Q2 is supplied to the primary side series resonant circuit, which makes the switching operation of the primary side series resonant circuit a current resonant operation.
On the secondary side of the transformer T, the center tap formed at the center point of the secondary coil N2 is connected with the secondary side ground. In addition, rectifier diodes D3 and D4, and a smoothing capacitor Co connected as shown in FIG. 1 form a secondary side full-wave rectifier. An alternating voltage excited on the secondary coil N2 is rectified and smoothed by this secondary side full-wave rectifier. A secondary side DC voltage Vout is generated as a voltage across the smoothing capacitor Co, and supplied to a load.
In addition, the secondary side DC voltage Vout is branched and supplied to the error amplifier 12 in the control circuit 9. In the error amplifier 12, the level of the secondary side DC voltage Vout and the predefined level of a reference voltage Vref are compared with each other, and an error signal having the level corresponding to an error between two levels is generated and supplied to the oscillator 10 via a photocoupler 13. The photocoupler 13 is provided for isolating the primary side from the secondary side in order to accurately feed back the error signal from the secondary side to the oscillator 10 that is supposed to be disposed on the primary side. A resistor Ro is disposed to adjust a current to be injected into a photodiode in the photocoupler 13 in accordance with the error signal.
The oscillator 10 is a variable-frequency oscillator that changes its oscillating frequency in accordance with the error signal. The amount of energy transmitted from the primary side to the secondary side changes as the switching frequency of the FET Q1 and FET Q2 changes, with the result that the level of the secondary side DC voltage Vout is variably controlled. As a result, the secondary side DC output voltage can be stabilized by the above-described control system.
To put it concretely, the stabilization control works such that the switching frequency is made low when the level of the secondary side DC voltage Vout lowers. As a result, the amount of energy transmitted to the secondary side increases and the secondary side DC voltage Vout rises. When the level of the secondary side DC voltage Vout rises, the switching frequency is made high, with the result that the amount of energy transmitted to the secondary side decreases and the secondary side DC voltage Vout lowers. Alternatively, in stead of the oscillator 10, a pulse-width modulation circuit can be used to stabilize the output voltage by changing the pulse width of its output pulse.
FIG. 2 shows a circuit including the FET Q1 and FET Q2 as a part of the entire circuit shown in FIG. 1. FIG. 3 shows the waveforms of the drive signals SG1 and SG2, the waveforms of the currents IQ1, IQ2, and IL, and the waveform of the voltage VC1 across the resonant capacitor C1 at the time when the power supply for the switching power supply circuit is in a stable state (or when the switching power supply circuit is in a normal operation state). Here, the currents IQ1 and IQ2 represent currents that flow through the FET Q1 and FET Q2 respectively, and the current IL represents a current that flows through the resonant circuit.
The drive circuit 11 supplies the drive signals SG1 and SG2 to the gates of the FET Q1 and FET Q2 respectively as shown in FIG. 3A and FIG. 3B. The FET Q1 is ON during the time period when the drive signal SG1 is in the high level of a positive polar pulse, and the FET Q1 is OFF during the time period when the drive signal SG1 is in the low level. The same is equally true of the FET Q2 and the drive signal SG2.
The operation of the above circuit including the FET Q1 and FET Q2, which is in a normal operation state, will be described below. Firstly, at the start of the time period t1, because the drive signal SG1 becomes in the high level, the FET Q1 becomes ON, and the current IQ1 flows through a route from Q1, L1, and N1 to C1 as shown in FIG. 3C.
In the transient time period t2, the drive signal SG1 is in the low level, so both FET Q1 and FET Q2 are OFF. In this case, the IQ2 shown in FIG. 3D transiently flows through a route from D2, L1, and N1 to C1 in order to hold a resonant state formed by the leakage inductance component L1 and the resonant capacitor C1.
At the start of the time period t3, because the drive signal SG2 becomes in the high level, the FET Q2 becomes ON. In this instance, because the resonant state formed by the leakage inductance component L1 and the resonant capacitor C1 has been continued, the current IQ2 flows through a route from D2, L1, and N1 to C1 and a route from Q2, L1, and N1 to C1. However, owing to the resonance state formed by the leakage inductance component L1 and the resonant capacitor C1, the current IQ2 begins to flow reversely through a route from C1, N1, and L1 to Q2 over time.
The time period t4 is a transient time period, in which the drive signal SG2 is in the low level, so the FET Q2 is OFF. Because the FET Q1 is also OFF, the IQ1 flows through a route from C1, N1, and L1 to Q1 as shown in FIG. 3C. After the time period t4 is over, the operation of the circuit again returns to that in the time period t1.
The above-described switching power supply circuit is equipped with an overcurrent limiting circuit for protecting a power supply circuit or a load circuit. When an overcurrent is detected, the overcurrent limiting circuit stops the operation of the converter circuit.
FIG. 4 shows an example of a switching power supply circuit equipped with an overcurrent limiting circuit. The leakage inductance component L1, the output side smoothing capacitor Co, the load, the feedback loop, and the like in FIG. 1 are not shown in FIG. 4. In FIG. 5 and later figures, the above elements are not shown as well. The overcurrent limiting circuit 6 includes a comparator 6a. 
A current that flows the primary side of the transformer T is detected at a current detecting point 5, for example, as a voltage. The obtained voltage is sent to the comparator 6a, and is compared with the voltage value of a DC voltage supply 6b. When an overcurrent is detected, the detected voltage exceeds the voltage value of the DC voltage supply 6b, and the polarity of the output of the comparator 6a is reversed. The operation of the DC-DC converter 4 is stopped by the output of the comparator 6a. To put it concretely, the switching operation of the FET Q1 and FET Q2 is stopped. As a result, the output power supply to the load is cut off.
It is necessary for the switching power supply circuit to continue to supply power to the load as long as possible in the case where the voltage on the input side of the power supply circuit is lowered or cut off. The time during which the power supply circuit can continue to supply power after the input to the power supply circuit is cut off is called a holding time. The longer the holding time is, at the easier pace the load circuit can perform termination processing. Therefore, the longer the holding time is, the more desirable it is. For example, let's suppose that it takes about 20 ms the load circuit to detect the cutoff of the input, and it also takes about 20 ms the load circuit to transfer information from a volatile memory to an nonvolatile memory. In this case, it is necessary for the holding time to be more than 40 ms.
In the case where the input is cut off, power continues to be supplied to the load circuit by energy stored inside the power supply circuit. The energy inside the power supply circuit is stored in the blocking capacitor Ci. The terminal voltage across the capacitor Ci decreases as part of the energy stored in the capacitor Ci is pulled out. Therefore, in order for a constant amount of energy to be pulled out, it is necessary to take more current out from the capacitor Ci when taking the equation “current=power/voltage” into consideration as the voltage across the capacitor Ci decreases.
In an existing power supply circuit, because the overcurrent limiting circuit 6 operates as described above, the operation of the DC-Dc converter 4 is stopped. As a result, the operation of the power supply circuit is stopped, and the power supply to the load circuit is cut off. As described above, there is a problem in that it may be difficult to prolong the holding time owing to the stoppage of the overcurrent limiting circuit 6.
Techniques to change the threshold of the overcurrent limiting circuit are disclosed in Japanese Unexamined Patent Application Publication 07-312861, Japanese Unexamined Patent Application Publication 2004-166440, and Japanese Unexamined Patent Application Publication 2002-51540.